All-Digital Phase Locked Loop (ADPLL) -A Review
نویسندگان
چکیده
--The All-Digital Phase-Locked Loop (ADPLL) is digital electronic circuit that are used in modern electronic communication systems like frequency synthesizer, modulator/demodulator etc. This paper presents a review of various ADPLL techniques. The range of input frequency of ADPLL is 40 to 98 MHz; the output frequency may be up to 2.92 to 4 GHz range. The components of ADPLL such as phase detector, loop filter, Voltage Controlled Oscillator have been discussed in detail. Various problems in Digital PLL like noise, leakage, parasitic element etc. can be removed with the help of All-Digital PLL. Various parameters of ADPLL like power consumption, jitter, input and output frequency have also been compared. Now a days, processors using ADPLL having frequency in GHz range are being used in mobile communication to increase the speed of the system. Keywords---Phase-Locked Loop (PLL), Phase detector (PD), Loop filter, Voltage Controlled Oscillator (VCO), Time to digital converter (TDC), Digital PLL (DPLL), All Digital PLL (ADPLL).
منابع مشابه
An All-Digital Phase-Locked Loop for High-Speed Clock Generation
An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented in this brief. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3m one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 refer...
متن کاملA Frequency Synthesis of All Digital Phase Locked Loop
All Digital Phase locked loops (ADPLL) plays a major role in System on Chips (SoC). Many EDA tools are used to design such complicated ADPLLs. It operates on two modes such as frequency acquisition mode and phase acquisition mode. Frequency acquisition mode is faster compared to Phase acquisition, hence frequency synthesis is performed. The CMOS technology is used to design such a complex desig...
متن کاملLow Jitter ADPLL based Clock Generator for High Speed SoC Applications
An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. ...
متن کاملA 0.65–1.35 GHz synthesizable all-digital phase locked loop with quantization noise suppressing time-to-digital converter
This paper presents a new quantization noise suppression method for a time-to-digital converter (TDC) and proposes an all-digital phase-locked loop (ADPLL) architecture using only standard cell logic gates. Using a new multiple input multiple output (MIMO) quantization noise suppression method provides an order of √ 2N improvement in TDC resolution with N parallel TDC channels. Suppressed noise...
متن کاملADPLL design parameters determinations through noise modeling
This paper presents a methodology to determine all-digital phase-locked loop (ADPLL) circuit variables based on required design specifications, including output phase noise, fractional spur and locking time. An analytical model is developed to characterize the effects of different noise sources on ADPLL output phase noise and fractional spur. Applying the proposed noise model, circuit variables...
متن کامل